1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a signal line drive circuit of a semiconductor device.
2. Description of the Related Art
As the degree of integration of semiconductor devices increases, the size of the various devices making up the internal structure of device chips decreases. This increase in integration is thus accompanied by a lengthening of the signal lines through which signals are transmitted (i.e., input and output lines and data lines), which in turn increases the load of the signal lines. It has therefore become important to reduce any delay time generated in the signal lines due to the relatively large load by speeding up the signal line drive function to obtain a high speed operation of the semiconductor device. In other words, the transmission characteristics of the signal line connecting the circuits should be improved to allow for a high speed operation.
FIG. 1 is a circuit diagram of a conventional drive circuit for driving a signal line having a large load.
Referring to FIG. 1, a driver 1 includes one set of series connected inverting buffers I1 and I2 and drives a signal line having a large load connected to an output port thereof, namely, loads 3 and 5. Here, the size of the inverting buffer I2 is appropriately designed for driving the signal line having the large loads 3 and 5. When an output signal of the driver 1 is transmitted through the signal line, the delay time generated by the loads 3 and 5 of the signal line is determined by multiplying together the resistance R and the capacitance C of the load. Therefore, since the signal line is physically long in a highly integrated device and thus the resistance R and the capacitance C of the signal line are relatively large, the conventional drive circuit of FIG. 1 suffers a drawback in that the delay time of the signal transmitted through the signal line increases and the slope of the V-time curve (defined by the rise in voltage with respect to time) becomes flatter.
FIG. 2 is a circuit diagram of another conventional drive circuit for driving a high-load signal line.
The circuit of FIG. 2 includes a second driver 9 located near the physical center (N) of the signal line between loads 3 and 5. Namely, the first driver 7 drives the load 3 and the second driver 9 drives the load 5. The first driver 7 is comprised of series connected inverting buffers I3 and I4, and the second driver 9 is comprised of series connected inverting buffers I5 and I6. The conventional drive circuit of FIG. 2 has an advantage in that the slope of the V-time curve of the signal transmitted through the signal line is steepened, but nevertheless suffers a disadvantage in that there is a time lapse cause by buffering that takes place in the second driver 9.
FIG. 4 shows simulated results of the conventional signal line drive circuits of FIGS. 1 and 2, and the signal line drive circuit according to the present invention of FIG. 3 which will be described later. Here, IN denotes an input signal and OUT1, OUT2, and OUT3 denote the output signals of the drive circuits of FIGS. 1, 2, and 3, respectively. FIG. 4 illustrates the results of performing a simulation in the drive circuits of FIGS. 1, 2, and 3 using loads and drivers of the same size. That is, the simulation results were obtained under the following conditions: the size of the inverting buffer 12 of FIG. 1 was equal to the sum of the inverting buffers I4 and I6 of FIG. 2 and the sum of the inverting buffers I8 and I9 of FIG. 3; the widths of a PMOS transistor and an NMOS transistor were 300 .mu.m and 150 .mu.m, respectively; the resistance of the combined load (the load 3+the load 5) of the signal line was 800.OMEGA.; the load capacitance was 4 pF; and the power supply voltage V.sub.cc was 2V.
As shown in the simulated results of FIG. 4, the output signal OUT2 of the drive circuit of FIG. 2 reaches V.sub.cc /2 (about 1V) faster than the output signal OUT1 of the drive circuit of FIG. 1 by a time difference .DELTA.1. However, the output signal OUT1 of the drive circuit of FIG. 1 reaches a voltage in the RO voltage region faster than the output signal OUT2 of the drive circuit of FIG. 2, i.e., the voltage region in which the voltage level of the output signals is lower than V.sub.cc /2. This is due to the the buffering time in the second driver 9 of FIG. 2 which causes the enable starting point S2 of the output signal OUT2 to be delayed by t1 compared to the enable starting point S1 of the output signal OUT1.
In the conventional signal line drive circuits of FIGS. 1 and 2, when a signal is transmitted through the high-load signal line at,a high speed, an erroneous operation can result since the high load is accompanied by an increase in the delay time of the signal transmitted through the signal line and a flattening of the slope of the V-time curve.